Static power reduction in caches using deterministic naps
AssigneeTexas Instruments Incorporated
InventorsOluleye Olorode, Mehrdad Nourani
Life of this patent
Estimating the term…
Abstract
Disclosed embodiments relate to a dNap architecture that accurately transitions cache lines to full power state before an access to them. This ensures that there are no additional delays due to waking up drowsy lines. Only cache lines that are determined by the DMC to be accessed in the immediate future are fully powered while others are put in drowsy mode. As a result, we are able to significantly reduce leakage power with no cache performance degradation and minimal hardware overhead, especially at higher associativities. Up to 92% static/Leakage power savings are accomplished with minimal hardware overhead and no performance tradeoff.
Claims20
A cache memory system, comprising:
- a memory including cache lines;
- and
- a controller coupled to the memory, the controller configured to:
- receive a memory access request;
- determine a set of cache lines associated with the memory access request;
- and
- transition the set of cache lines from a low power state to an operating state.
A method, comprising:
- receiving, by a memory controller, a memory access request associated with a memory;
- determining, by the memory controller, a set of cache lines associated with the memory access request;
- and
- transitioning, by the memory controller, the set of cache lines from a low power state to an operating state.
Dependencies are inferred from the claim text.