US 2022/0091452 A1Published application

Driver array substrate, display panel and display device

AssigneeHkc Corporation Limited

InventorsWenqin ZHAO, Wei LI

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Abstract

Disclosed is a driver array substrate including a substrate, a plurality of first sub-pixels, a plurality of second sub-pixels, and a plurality of common electrodes; each first sub-pixel includes a first thin film transistor; each second sub-pixel includes a second thin film transistor; each first sub-pixel further includes a first storage capacitor, a first end of the first storage capacitor is connected to a drain of a corresponding first thin film transistor, and a second end thereof is connected to a first end of a corresponding common electrode; each second sub-pixel further includes a second storage capacitor, a capacitance value of the second storage capacitor is less than that of the first storage capacitor, a first end of the second storage capacitor is connected to a drain of a corresponding second thin film transistor, a second end thereof is connected to a first end of a corresponding common electrode.

Claims20

Dependent claims

A driver array substrate, comprising a substrate, a plurality of first sub-pixels, a plurality of second sub-pixels, and a plurality of common electrodes provided on the substrate, each first sub-pixel comprising a first thin film transistor, each second sub-pixel comprising a second thin film transistor, wherein the first sub-pixels and the second sub-pixels are arranged in both a first direction and a second direction of the substrate;

the first sub-pixels and the second sub-pixels are sequentially arranged alternately in the first direction, and the first sub-pixels and the second sub-pixels are sequentially alternately arranged in the second direction;
each first sub-pixel further comprises a first storage capacitor, a first end of the first storage capacitor is connected to a drain of a corresponding first thin film transistor, and a second end of the first storage capacitor is connected to a first end of a corresponding common electrode;
each second sub-pixel further comprises a second storage capacitor, a capacitance value of the second storage capacitor is less than that of the first storage capacitor, a first end of the second storage capacitor is connected to a drain of a corresponding second thin film transistor, a second end of the second storage capacitor is connected to a first end of a corresponding common electrode;
a second end of each common electrode is configured to be connected to a same potential.

1 more element

the first sub-pixels and the second sub-pixels are sequentially arranged alternately in the first direction, and the first sub-pixels and the second sub-pixels are sequentially arranged alternately in the second direction;
each first sub-pixel further comprises a first storage capacitor, a first end of the first storage capacitor is connected to a drain of a corresponding first thin film transistor, and a second end of the first storage capacitor is connected to a gate of a thin film transistor of an adjacent sub-pixel;
each second sub-pixel further comprises a second storage capacitor, a capacitance value of the second storage capacitor is less than that of the first storage capacitor, a first end of the second storage capacitor is connected to a drain of a corresponding second thin film transistor, and a second end of the second storage capacitor is connected to a gate of a thin film transistor of an adjacent sub-pixel.

Dependencies are inferred from the claim text.