Spi nor memory with optimized read and program operation
AssigneeIntegrated Silicon Solution, (Cayman) Inc.
InventorSungJin Han
Life of this patent
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Abstract
A serial NOR memory device receives serial input data using a single data rate (SDR) mode and transmits serial output data using a double data rate (DDR) mode. In some embodiments, a serial NOR memory device includes an input-output circuit including a transceiver coupled to receive a clock signal and serial input data and to provide serial output data. The transceiver is configured to receive serial input data using the single data rate mode and is configured to transmit serial output data using the double data rate mode.
Claims15
A serial NOR memory device, comprising:
- an input-output circuit comprising a transceiver coupled to receive a clock signal on a clock input terminal and a serial input data on serial data input terminal, the transceiver further coupled to transmit serial output data on a serial data output terminal,
- wherein the transceiver is configured to receive serial input data on the serial data input terminal using a single data rate mode and is configured to transmit serial output data onto the serial data output terminal using a double data rate mode.
A method in a serial NOR memory device comprising a memory cell array, comprising:
- receiving a clock signal;
- receiving a command signal in a single data rate mode;
- receiving an address signal in the single data rate mode;
- in response to the command signal being a read command, retrieving read data from the memory cell array in response to the address signal;
- and
- transmitting the read data in a double data rate mode.
Dependencies are inferred from the claim text.