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US 2022/0071016 A1Published application
Circuit board and method of manufacturing the same
AssigneeLG Innotek Co., Ltd.
InventorsMin Young HWANG, Byeong Kyun Choi, Jin Seok Lee, Moo Seong Kim
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Abstract
A circuit board according to an embodiment includes an insulating layer; and a circuit pattern disposed on the insulating layer, wherein the circuit pattern includes a copper foil layer disposed on the insulating layer, a first plating layer disposed on the copper foil layer, and a second plating layer disposed on the first plating layer, and wherein the copper foil layer has a thickness in a range of 2 μm to 5 μm.
Claims20
A circuit board comprising:
- an insulating layer;
- and
- a circuit pattern disposed on the insulating layer,
- wherein the circuit pattern includes:
- a copper foil layer disposed on the insulating layer,
- a first plating layer disposed on the copper foil layer, and
- a second plating layer disposed on the first plating layer, and
- wherein the copper foil layer has a thickness in a range of 2 μm to 5 μm.
5 more elements
A method of manufacturing a circuit board comprising:
- preparing a resin coated copper (RCC) including an insulating layer which is a composite of a resin and a filler, and a copper foil layer disposed on the insulating layer;
- forming a via hole passing through the insulating layer;
- removing a filler exposed through an inner wall of the via hole;
- forming a first plating layer on an inner wall of the via hole from which the filler is removed, and
- forming a second plating layer filling the via hole on the first plating layer,
- wherein a recess corresponding to the removed filler is formed on the inner wall of the via hole, and
- wherein the recess has a depth in a range of 0.5 μm to 1.0 μm.
4 more elements
A method of manufacturing a circuit board comprising:
- preparing a resin coated copper (RCC) including an insulating layer which is a composite of a resin and a filler, and a copper foil layer disposed on the insulating layer;
- forming a via hole passing through the insulating layer;
- surface-treating the resin and filler exposed through the inner wall of the via hole by using plasma, wherein the inner wall of the via hole has a surface roughness (Ra) in a range of 0.5 μm to 1.0 μm by the surface treatment;
- forming a first plating layer on an inner wall of the surface-treated via hole, and forming a second plating layer filling the via hole on the first plating layer.
1 more element
Dependencies are inferred from the claim text.