Symbol and timing recovery apparatus and related methods
AssigneeTexas Instruments Incorporated
InventorsRaghu Ganesan, Saravanakkumar Radhakrishnan, Gaurav Aggarwal
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Abstract
An example apparatus includes: a feed forward equalizer (FFE) with a FFE output, adder circuitry with a first adder input, a second adder input, and a first adder output, the first adder input coupled to the FFE output, a multiplexer (MUX) with a first MUX input, a second MUX input, and a MUX output, the first MUX input coupled to the first adder output, the second MUX input coupled to the FFE output, a decision feedback equalizer (DFE) with a DFE output coupled to the second adder input, and a timing error detector (TED) with a first TED input coupled to the MUX output.
Claims25
An apparatus comprising:
- a feed forward equalizer (FFE) with a FFE output;
- adder circuitry with a first adder input, a second adder input, and a first adder output, the first adder input coupled to the FFE output;
- a multiplexer (MUX) with a first MUX input, a second MUX input, and a MUX output, the first MUX input coupled to the first adder output, the second MUX input coupled to the FFE output;
- a decision feedback equalizer (DFE) with a DFE output coupled to the second adder input;
- and
- a timing error detector (TED) with a first TED input coupled to the MUX output.
A receiver operable to receive a communication signal including a plurality of symbols, the receiver comprising:
- memory including instructions stored in the memory;
- a processor coupled to the memory and operable to execute the instructions to at least:
- detect one or more first symbols of the plurality of the symbols in the communication signal based on a first phase of a sampling clock;
- determine a second symbol of the plurality of the symbols in the communication signal based on the one or more first symbols;
- generate a voltage corresponding to a timing phase offset, the voltage based on the second symbol;
- in response to the voltage satisfying a threshold, generate a control signal based on the second symbol;
- and
- adjust the first phase to a second phase based on the control signal.
At least one non-transitory computer readable storage medium comprising instructions that, when executed, cause a processor to at least:
- detect one or more first symbols of a digital signal based on a first phase of a sampling clock;
- determine a second symbol based on the one or more first symbols;
- generate a voltage corresponding to a timing phase offset, the voltage based on the second symbol;
- in response to the voltage satisfying a threshold, generate a control signal based on the second symbol;
- and
- adjust the first phase to a second phase based on the control signal.
Dependencies are inferred from the claim text.