Method for Cryptographic Engine to Interface with an Arbitrary Number of Processor Cards in a Scalable Environment

A circuit card assembly comprising:

• at least one processor defining a plurality of interface ports and a plurality of cryptographic ports;
• and
• at least one field programmable gate array configured to host a plurality of cryptographic functions, the at least one field programmable gate array defining:
• a static region defining a plurality of transport layer interfaces;
• and
• a dynamic region comprising at least one switch bank configured to connect one or more of the transport layer interfaces to one or more of the plurality of interface ports and plurality of cryptographic ports,
• wherein:
• the at least one processor is configured to:
• establish a communication channel between a first transport layer interface and a second transport layer interface via the at least one switch bank;
• and
• apply one or more of the plurality of cryptographic functions to the communication channel.