Parity interleaving apparatus for encoding fixed-length signaling information, and parity interleaving method using same
AssigneeElectronics and Telecommunications Research Institute
InventorsSung-Ik PARK, Sun-Hyoung KWON, Jae-Young LEE, Heung-Mook KIM
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Abstract
A parity interleaving apparatus and method for fixed length signaling information are disclosed. A parity interleaving apparatus according to an embodiment of the present invention includes a processor configured to generate a parity bit string for parity puncturing by segmenting parity bits of an LDPC codeword whose length is 16200 and whose code rate is 3/15, into a plurality of groups, and group-wise interleaving the groups using an order of group-wise interleaving; and memory configured to provide the parity bit string for parity puncturing to a parity puncturing unit.
Claims10
An inverse parity interleaving apparatus, comprising:
- memory configured to store restored parity values;
- and
- a processor configured to generate deinterleaved parity values corresponding to parity bits of an LDPC codeword whose length is 16200 and whose code rate is 3/15 by segmenting the restored parity values into a plurality of groups, and group-wise de-interleaving the groups corresponding to an order of group-wise interleaving.
An inverse parity interleaving method, comprising:
- storing restored parity values;
- and
- generating deinterleaved parity values corresponding to parity bits of an LDPC codeword whose length is 16200 and whose code rate is 3/15 by segmenting the restored parity values into a plurality of groups, and group-wise de-interleaving the groups corresponding to an order of group-wise interleaving.
Dependencies are inferred from the claim text.