Successive approximation register analog-to-digital converter with embedded filtering
AssigneeTexas Instruments Incorporated
InventorsDebapriya SAHU, Pranav SINHA, Meghna AGRAWAL
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Abstract
A successive approximation register (SAR) analog-to-digital converter includes a capacitive digital-to-analog converter (CDAC), a comparator, and a SAR control circuit. The comparator is coupled to an output of the CDAC. The SAR control circuit is coupled to an input of the CDAC and to an output of the comparator. The SAR control circuit is configured to provide a feedback signal to the CDAC. The CDAC is configured to apply the feedback signal to form an infinite impulse response filter.
Claims20
A successive approximation register (SAR) analog-to-digital converter (ADC), comprising:
- a capacitive digital-to-analog converter (CDAC) comprising a plurality of capacitors;
- a comparator comprising an input coupled to an output of the CDAC;
- a SAR control circuit comprising:
- a digital sample register;
- a successive approximation register;
- a selector circuit comprising:
- a first input coupled to an output of the digital sample register;
- a second input coupled to an output of the successive approximation register;
- and
- an output coupled to an input of the CDAC;
- wherein:
- the SAR control circuit is configured to, in a first sample acquisition cycle:
- store, on the capacitors of the CDAC, an analog input signal to be digitized;
- and
- store, on the capacitors of the CDAC, bits of a digital sample value representing a sample of the analog input signal stored on the capacitors of the CDAC in a second sample acquisition cycle;
- and
- the second sample acquisition cycle precedes the first sample acquisition cycle.
A successive approximation register (SAR) analog-to-digital converter (ADC), comprising:
- a capacitive digital-to-analog converter (CDAC);
- a comparator coupled to an output of the CDAC;
- and
- a SAR control circuit coupled to an input of the CDAC and an output of the comparator, and configured to, in a sample acquisition phase of the SAR ADC, provide a feedback signal to the CDAC;
- wherein:
- the feedback signal comprises a digital sample value generated by the SAR ADC in last completed digitization phase;
- and
- the CDAC is configured to apply the feedback signal to form an infinite impulse response filter.
A wake-up receiver comprising:
- a mixer circuit configured to down convert a received radio frequency signal;
- a successive approximation register (SAR) analog-to-digital converter (ADC) coupled to the mixer circuit and configured to digitize an output signal of the mixer circuit, and comprising:
- a capacitive digital-to-analog converter (CDAC);
- a comparator coupled to the CDAC;
- a SAR control circuit coupled to the CDAC and the comparator, and configured to, in a sample acquisition phase of the SAR ADC, sum, in the CDAC, the output signal of the mixer circuit and a feedback signal based on a digital sample value generated by the SAR ADC in a last completed digitization phase.
Dependencies are inferred from the claim text.