Digital pll circuitry

A digital PLL circuitry comprising:

• a phase difference arithmetic circuitry configured to arithmetically determine and output a phase difference between an input clock signal and an output clock signal;
• a first control code generation circuitry configured to generate a first control code for controlling an oscillation frequency based on both the phase difference and a frequency control input that is a control target frequency of the output clock signal, and further configured to output the first control code;
• a second control code generation circuitry configured to execute a sequence to generate and output a second control code for controlling the oscillation frequency;
• a selection circuitry configured to select and output one of the first control code and the second control code as a selection control code, wherein after execution of the sequence by the second control code generation circuitry ends, the selection circuitry selects and outputs the lower one of the first control code and the second control code as the selection control code;
• and
• a digitally controlled oscillator configured to output the output clock signal at the oscillation frequency corresponding to the selection control code.

A digital PLL circuitry comprising:

• a phase difference arithmetic circuitry configured to arithmetically determine and output a phase difference between an input clock signal and an output clock signal;
• a first control code generation circuitry configured to generate a first control code for controlling an oscillation frequency based on both the phase difference and a frequency control input that is a control target frequency of the output clock signal, and further configured to output the first control code;
• a second control code generation circuitry configured to execute a startup sequence at startup of the digital PLL circuitry to generate and output a second control code for controlling the oscillation frequency;
• a selection circuitry configured to select and output one of the first control code and the second control code as a selection control code, wherein after the startup sequence of the second control code generation circuitry ends, the selection circuitry selects and outputs the lower one of the first control code and the second control code as the selection control code;
• and
• a digitally controlled oscillator configured to output the output clock signal at the oscillation frequency corresponding to the selection control code.