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US 2022/0069825 A1Published application
Integrated circuit
AssigneeSK hynix Inc.
InventorWoongrae KIM
Life of this patent
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Abstract
An integrated circuit including: a clock generation circuit configured to generate first and second divided clock signals by dividing an external clock signal; and a command generation circuit configured to synchronize and decode an external command signal based on a divided clock signal of the first and second divided clock signals, which is synchronized with a chip select signal.
Claims15
An integrated circuit comprising:
- a clock generation circuit configured to generate first and second divided clock signals by dividing an external clock signal;
- and
- a command generation circuit configured to synchronize and decode an external command signal based on a divided clock signal of the first and second divided clock signals, which is synchronized with a chip select signal.
Dependencies are inferred from the claim text.