Transmitter and receiver for low power input/output and memory system including the same

A memory system comprising:

• a transmitter configured to output write data to be stored in a memory device or read data retrieved from the memory device;
• a channel configured to transmit the write data or the read data;
• and
• a receiver configured to receive the write data or the read data,
• wherein the transmitter includes:
• a multiplexer configured to generate a plurality of time-interleaved data signals based on a plurality of input data signals and multi-phase clock signals, the plurality of input data signals being input in parallel, each of the plurality of input data signals having at least two voltage levels that are different from each other;
• control logic configured to generate a plurality of control signals based on the plurality of time-interleaved data signals, at least one of the plurality of control signals having a voltage level that is temporarily boosted;
• and
• a voltage mode driver configured to generate an output data signal based on the at least one pull-down control signal and the plurality of pull-up control signals, the output data signal having at least three voltage levels that are different from each other,
• wherein the receiver includes:
• a first flip-flop configured to receive the output data signal, a first clock signal, a first reference voltage and a first selection signal, form a second reference voltage different from the first reference voltage based on the first reference voltage and the first selection signal, generate a first data signal based thereon, the first data signal being at least one of the plurality of input data signals having at least two voltage levels that are different from each other, and provide the first data signal as a second selection signal;
• and
• a second flip-flop configured to receive the output data signal, a second clock signal, the first reference voltage and the second selection signal, generate a second data signal based thereon, the second data signal being at least one of the plurality of input data signals having at least two voltage levels that are different from each other, the second clock signal being different from the first clock signal, and to provide the second data signal as the first selection signal,
• wherein the plurality of input data signals, the output data signal and the first and second data signals correspond to the write data or the read data.