US 2022/0069813 A1Published application

Buffer circuit

AssigneeSK hynix Inc.

InventorsSun Ki Cho, Dong Uc Ko, Yang Ho Sur, Jun Yong Song, Sung Gil Jang, Hae Kang Jung, Min Sung Cheon, Chang Kyu Choi, Tae Jin Hwang

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Abstract

A buffer circuit configured to receive first and second input signals through first and second input transistors coupled to a first power voltage node, output a first output signal through a first output node and a second output signal through a second output node based on the first and second input signals. A load circuit is coupled among the first output node, the second output node, and a second power voltage node and a resistance value is adjusted based on at least one of the first and second output signals.

Claims29

Dependent claims

A buffer circuit comprising:

a first input transistor coupled between a first power voltage node and a second output node, and configured to change a voltage level of the second output node based on a first input signal;
a second input transistor coupled between the first power voltage node and a first output node, and configured to change a voltage level of the first output node based on a second input signal;
a first load resistor coupled between the second output node and a second power voltage node;
a second load resistor coupled between the first output node and the second power voltage node;
and
at least one switching transistor configured to couple the first load resistor and the second load resistor to each other in parallel based on the at least one of a first output signal from the first output node and a second output signal from the second output node.

3 more elements

A buffer circuit comprising:

a first input transistor coupled between a first power voltage node and a second output node, and configured to change a voltage level of the second output node based on a first input signal;
a second input transistor coupled between the first power voltage node and a first output node, and configured to change a voltage level of the first output node based on a second input signal;
a load control circuit configured to generate a first load control signal and a second load control signal based on a first output signal output from the first output node and a second output signal output from the second output node;
a first load resistor including one end coupled to the second output node and the other end coupled to the second power voltage node;
a second load resistor including one end coupled to the first output node and the other end coupled to the second power voltage node;
a first switching transistor configured to couple the one end of the first load resistor and the one end of the second load resistor to each other based on the first load control signal;
and
a second switching transistor configured to couple the one end of the first load resistor and the one end of the second load resistor to each other based on the second load control signal.

5 more elements

Dependencies are inferred from the claim text.

Facts

Application: 17/171,719Filed 9 Feb 2021
Priority: KR 10-2020-01114352 Sep 2020
Published: 3 Mar 2022
Term ends: Not estimatedThe source records don’t support an estimate.

Classification8 codes

H03K 5/02
Shaping pulses: by amplifying
H03K 5/04
Shaping pulses: by increasing duration; by decreasing duration
H03F 3/45076
With semiconductor devices only: characterised by the way of implementation of the active amplifying circuit in the differential amplifier
H03F 3/45183
Using MOSFET transistors as the active amplifying circuit: long tailed pairs