Latch circuit, memory device and method

A memory device, comprising:

• a memory cell;
• and
• a control circuit coupled to control an operation of the memory cell, the control circuit comprising:
• a latch clock generator configured to generate a latched clock signal based on a clock signal and an enable signal;
• and
• an input latch coupled to the latch clock generator to receive the latched clock signal, the input latch configured to generate a latched output signal based on the latched clock signal and an input signal,
• wherein the enable signal corresponds to at least one of
• a chip enable signal to enable or disable the memory device, or
• a write enable signal to enable or disable writing to the memory cell.

A method of operating a memory device having a memory cell, the method comprising:

• generating an internal clock signal based on a clock signal and a first enable signal;
• generating a latched clock signal based on the internal clock signal and a second enable signal;
• and
• generating a latched output signal for controlling an operation of the memory cell based on the latched clock signal and an input signal,
• wherein
• in said generating the latched clock signal,
• in response to the second enable signal having a disabling logic level, a logic level of the latched clock signal is set to a corresponding disabling logic level regardless of the clock signal and the first enable signal, and
• in said generating the latched output signal,
• in response to the corresponding disabling logic level of the latched clock signal, a logic level of the latched output signal is held unchanged regardless of the input signal.