Motor control apparatus

A motor control apparatus configured to control a three-phase brushless motor, the three-phase brushless motor including a motor rotor, a first stator coil including a first u phase, a first v phase, and a first w phase, and a second stator coil including a second u phase, a second v phase, and a second w phase, the motor control apparatus comprising:

• a first driving circuit including a first bridge circuit including a first inverter, the first driving circuit being configured to control driving of the first inverter based on a first u phase duty ratio signal, a first v phase duty ratio signal, or a first w phase duty ratio signal to control power to be supplied to the first stator coil;
• a second driving circuit including a second bridge circuit including a second inverter, the second driving circuit being configured to control driving of the second inverter based on a second u phase duty ratio signal, a second v phase duty ratio signal, or a second w phase duty ratio signal to control power to be supplied to the second stator coil;
• a first current sensor configured to detect a first direct-current bus current flowing in a first direct-current bus of the first driving circuit and output it as a first detected current signal;
• a second current sensor configured to detect a second direct-current bus current flowing in a second direct-current bus of the second driving circuit and output it as a second detected current signal;
• and
• a microcomputer including an instruction current generation portion, a current control portion, a PWM duty ratio signal generation portion, a first detected current correction portion, a second detected current correction portion, and an offset correction value storage portion,
• wherein the instruction current generation portion generates a first instruction signal for controlling driving of the three-phase brushless motor,
• wherein the current control portion includes a first current control portion and a second current control portion,
• wherein the first current control portion generates a first second instruction signal based on the first instruction signal, a first u phase detected current signal, a first v phase detected current signal, and a first w phase detected current signal,
• wherein the second current control portion generates a second second instruction signal based on the first instruction signal, a second u phase detected current signal, a second v phase detected current signal, and a second w phase detected current signal,
• wherein the PWM duty ratio signal generation portion includes a first PWM duty ratio signal generation portion and a second PWM duty ratio signal generation portion,
• wherein the first PWM duty ratio signal generation portion generates the first u phase duty ratio signal, the first v phase duty ratio signal, or the first w phase duty ratio signal based on the first second instruction current signal, the first u phase duty ratio signal, the first v phase duty ratio signal, and the first w phase duty ratio signal being signals of duty ratios with respect to the first u phase, the first v phase, and the first w phase, respectively,
• wherein the second PWM duty ratio signal generation portion generates the second u phase duty ratio signal, the second v phase duty ratio signal, or the second w phase duty ratio signal based on the second second instruction current signal, the second u phase duty ratio signal, the second v phase duty ratio signal, and the second w phase duty ratio signal being signals of duty ratios with respect to the second u phase, the second v phase, and the second w phase, respectively,
• wherein the first detected current correction portion generates the first u phase detected current signal, the first v phase detected current signal, or the first w phase detected current signal by correcting a first u phase detected current, a first v phase detected current, or a first w phase detected current based on a maximum phase offset correction value or a minimum phase offset correction value,
• wherein the first u phase detected current, the first v phase detected current, and the first w phase detected current are currents corresponding to currents generated based on the first detected current signal and flowing in the first u phase, the first v phase, and the first w phase, respectively,
• wherein the second detected current correction portion generates the second u phase detected current signal, the second v phase detected current signal, or the second w phase detected current signal by correcting a second u phase detected current, a second v phase detected current, or a second w phase detected current based on the maximum phase offset correction value or the minimum phase offset correction value,
• wherein the second u phase detected current, the second v phase detected current, and the second w phase detected current are currents corresponding to currents generated based on the second detected current signal and flowing in the second u phase, the second v phase, and the second w phase, respectively,
• wherein the offset correction value storage portion stores the maximum phase offset correction value and the minimum phase offset correction value, and
• wherein, assuming that a first maximum phase duty ratio signal and a first minimum phase duty ratio signal are a duty ratio signal for which power is supplied for a longest time and a duty ratio signal for which power is supplied for a shortest time among the first u phase duty ratio signal, the first v phase duty ratio signal, and the first w phase duty ratio signal, respectively, and a first maximum phase and a first minimum phase are a phase in which the first maximum phase duty ratio signal flows and a phase in which the first minimum phase duty ratio signal flows among the first u phase, the first v phase, and the first w phase, respectively,
• assuming that a first maximum phase detected current and a first minimum phase detected current are a detected current corresponding to the first maximum phase and a detected current corresponding to the first minimum phase among the first u phase detected current, the first v phase detected current, and the first w phase detected current, respectively,
• assuming that a second maximum phase duty ratio signal and a second minimum phase duty ratio signal are a duty ratio signal for which power is supplied for a longest time and a duty ratio signal for which power is supplied for a shortest time among the second u phase duty ratio signal, the second v phase duty ratio signal, and the second w phase duty ratio signal, respectively, and a second maximum phase and a second minimum phase are a phase in which the second maximum phase duty ratio signal flows and a phase in which the second minimum phase duty ratio signal flows among the second u phase, the second v phase, and the second w phase, respectively, and
• assuming that a second maximum phase detected current and a second minimum phase detected current are a detected current corresponding to the second maximum phase and a detected current corresponding to the second minimum phase among the second u phase detected current, the second v phase detected current, and the second w phase detected current, respectively,
• the maximum phase offset correction value corrects the first maximum phase detected current and the second maximum phase detected current, and
• the minimum phase offset correction value corrects the first minimum phase detected current and the second minimum phase detected current.