High-voltage tolerant, high-speed reverse current detection and protection for buck-boost converters

A zero crossing detection comparator circuit comprising:

• a negative input coupled to a ground of a buck-boost converter;
• a positive input coupled to an input of an inductor of the buck-boost converter;
• an output coupled to a gate of a first low-side switch of the buck-boost converter, wherein a value at the output is to be asserted in response to detecting a zero current flow through the first low-side switch while the buck-boost converter operates in buck mode;
• a first resistor coupled to the negative input;
• a second resistor coupled to the positive input, the first resistor having a substantially identical resistance as the second resistor;
• a first drain-extended n-type transistor (DENFET) coupled to the first resistor;
• a second DENFET coupled to the second resistor, wherein gates of the first and second DENFETs are coupled to a supply voltage;
• an operational amplifier comprising:
• a second positive input coupled to ground through a third resistor;
• a second negative input coupled to a bandgap voltage reference;
• and
• a second output;
• and
• a multi-stage amplifier coupled between the second output of the operational amplifier, the first and second DENFETs, and the output.

A reverse current detection comparator circuit comprising:

• a negative input coupled to an output of an inductor of a buck-boost converter;
• a positive input coupled to a voltage bus (Vbus) output of the buck-boost converter;
• an output coupled to a gate of a second high-side switch of the buck-boost converter, wherein a value at the output is to be asserted in response to detecting a zero current flow through the second high-side switch while the buck-boost converter operates in boost mode;
• a first resistor coupled to the negative input;
• a second resistor coupled to the positive input, the first resistor having a substantially identical resistance as the second resistor;
• a first drain-extended p-type transistor (DEPFET) coupled to the first resistor;
• a second DEPFET coupled to the second resistor, wherein gates of the first and second DEPFETs are coupled together;
• an operational amplifier comprising:
• a second positive input coupled to a ground through a third resistor;
• a second negative input coupled to a bandgap voltage reference;
• and
• a second output;
• and
• a multi-stage amplifier coupled between the second output of the operational amplifier, the first and second DEPFETs, and the output.