Heterojunction semiconductor device with low on-resistance

A heterojunction semiconductor device with low on-resistance comprising:

• a metal drain electrode, a substrate disposed on the metal drain electrode, a buffer layer disposed on the substrate, a current blocking layer disposed within the buffer layer, a gate structure disposed on the buffer layer and comprising a metal gate electrode, a metal source electrode disposed above the metal gate electrode, a first passivation layer disposed between the metal gate electrode and the metal source electrode, and a second passivation layer disposed between the metal gate electrode and the buffer layer;
• wherein the current blocking layer comprises a first-level annular current blocking layer, a second-level annular current blocking layer, and a third-level annular current blocking layer which are sequentially arranged from top to bottom, and symmetry centers of each of the layers are collinear;
• an annular inner opening of the first-level annular current blocking layer is larger than an annular inner opening of the second-level annular current blocking layer, and the annular inner opening of the second-level annular current blocking layer is larger than an annular inner opening of the third-level annular current blocking layer, presenting a trend of becoming smaller level by level.