Finfet and gate-all-around fet with selective high-k oxide deposition
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsTsung-Han TSAI, Jen-Hsiang LU, Shih-Hsun CHANG
Life of this patent
Estimating the term…
Abstract
A semiconductor device structure is provided. The semiconductor device structure includes a gate electrode layer formed over a semiconductor substrate. The semiconductor device structure also includes a gate dielectric layer formed between the gate electrode layer and the semiconductor substrate. In addition, the semiconductor device structure includes a first gate spacer having a hydrophobic surface that covers a first sidewall of the gate electrode layer. The first sidewall of the gate electrode layer extends along a first sidewall of the gate dielectric layer, so that the first sidewall of the gate dielectric layer is separated from the hydrophobic surface of the first gate spacer.
Claims20
A semiconductor device structure, comprising:
- a gate electrode layer formed over a semiconductor substrate;
- a gate dielectric layer formed between the gate electrode layer and the semiconductor substrate;
- and
- a first gate spacer having a hydrophobic surface that covers a first sidewall of the gate electrode layer, wherein the first sidewall of the gate electrode layer extends along a first sidewall of the gate dielectric layer, so that the first sidewall of the gate dielectric layer is separated from the hydrophobic surface of the first gate spacer.
A semiconductor device structure, comprising:
- an isolation feature formed over a semiconductor substrate with a fin structure extending in a first direction;
- an insulating gate-cut structure formed over the isolation feature and extending in the first direction, wherein the insulating gate-cut structure has a hydrophobic sidewall surface facing a sidewall surface of the fin structure;
- a gate electrode layer formed across the fin structure and extending in a second direction, wherein a portion of the gate electrode layer covers the hydrophobic sidewall surface of the insulating gate-cut structure and the sidewall surface of the fin structure;
- and
- a gate dielectric layer having a first portion covering a top surface of the isolation feature and a second portion extending from the first portion to cover the sidewall surface of the fin structure, wherein the first portion of the gate dielectric layer is separated from the hydrophobic sidewall surface of the insulating gate-cut structure by the portion of the gate electrode layer.
A semiconductor device structure, comprising:
- a fin structure formed over a semiconductor substrate and comprising two wire portions laterally extending in a first direction and vertically aligned to each other;
- an insulating layer formed over the semiconductor substrate and extending in the first direction, wherein the insulating layer has a hydrophobic sidewall surface;
- a gate electrode layer surrounding the two wire portions and extending in a second direction, wherein a portion of the gate electrode layer covers the hydrophobic sidewall surface of the insulating layer;
- and
- a gate dielectric layer having a first portion formed between the gate electrode layer and each of the two wire portions and a second portion separated from the first portion and covered by a bottom surface of the gate electrode layer, wherein the second portion of the gate dielectric layer is separated from the hydrophobic sidewall surface of the insulating layer by the portion of the gate electrode layer.
Dependencies are inferred from the claim text.