Semiconductor devices

A semiconductor device comprising:

• a first epitaxial pattern and a second epitaxial pattern in a first region of a substrate and separated from each other by a first distance;
• a third epitaxial pattern and a fourth epitaxial pattern in a second region of the substrate and separated from each other by a second distance;
• a first field insulating layer that covers a part of a sidewall of the first epitaxial pattern and a part of a sidewall of the second epitaxial pattern on the substrate between the first epitaxial pattern and the second epitaxial pattern;
• a second field insulating layer that covers a part of a sidewall of the third epitaxial pattern and a part of a sidewall of the fourth epitaxial pattern on the substrate between the third epitaxial pattern and the fourth epitaxial pattern;
• a first etch stop layer that extends along a top surface of the first field insulating layer, a sidewall of the first epitaxial pattern, and a sidewall of the second epitaxial pattern, and is in contact with the first field insulating layer;
• a second etch stop layer that extends along a top surface of the second field insulating layer, a sidewall of the third epitaxial pattern, and a sidewall of the fourth epitaxial pattern, and is in contact with the second field insulating layer;
• a first source/drain contact that is connected to the first epitaxial pattern and the second epitaxial pattern;
• and
• a second source/drain contact that is connected to the third epitaxial pattern and the fourth epitaxial pattern,
• wherein each of the first epitaxial pattern and the third epitaxial pattern includes a facet intersection point along a sidewall thereof where its width is at a maximum,
• wherein the first distance is smaller than the second distance, and
• wherein a depth from the facet intersection point of the first epitaxial pattern to the top surface of the first field insulating layer is smaller than a depth from the facet intersection point of the third epitaxial pattern to the top surface of the second field insulating layer.

A semiconductor device comprising:

• a first fin-shaped pattern in a PMOS region of a substrate, extending in a first direction, and defined by a fin trench;
• a second fin-shaped pattern in an NMOS region of the substrate, spaced apart from the first fin-shaped pattern in a second direction, extending in the first direction, and defined by the fin trench;
• a first epitaxial pattern on the first fin-shaped pattern, the first epitaxial pattern including a bottom surface connected to the first fin-shaped pattern;
• a second epitaxial pattern on the second fin-shaped pattern, the second epitaxial pattern separated from the first epitaxial pattern and including a bottom surface connected to the second fin-shaped pattern;
• a field insulating layer on the substrate, the field insulating layer covering a sidewall of the first fin-shaped pattern, a sidewall of the second fin-shaped pattern, a part of a sidewall of the first epitaxial pattern, and a part of a sidewall of the second epitaxial pattern;
• an etch stop layer extending along a top surface of the field insulating layer, the sidewall of the first epitaxial pattern, and the sidewall of the second epitaxial pattern, and in contact with the field insulating layer;
• and
• a source/drain contact on the first epitaxial pattern and the second epitaxial pattern, the source/drain contact connected to the first epitaxial pattern and the second epitaxial pattern,
• wherein the source/drain contact includes a first portion that vertically overlaps the first epitaxial pattern, and a second portion that vertically overlaps the second epitaxial pattern, and
• wherein a height from a bottom surface of the fin trench to a bottom surface of the first portion of the source/drain contact at a portion that overlaps the first fin-shaped pattern is greater than a height from the bottom surface of the fin trench to a bottom surface of the second portion of the source/drain contact at a portion that overlaps the second fin-shaped pattern.