US 2022/0069074 A1 · METHOD OF MANUFACTURING A SUPER JUNCTION STRUCTURE AND SUPER JUNCTION STRUCTURE

Abstract

A super junction structure includes a substrate, wherein the substrate has a first conductivity type. The super junction structure includes an epitaxial layer over the substrate, wherein the epitaxial layer has a second conductivity type opposite the first conductivity type. The super junction structure further includes a bury layer between the epitaxial layer and the substrate, wherein the bury layer has the second conductivity type. The super junction structure further includes a conductive pillar in the epitaxial layer, wherein the conductive pillar has the first conductivity type, sidewalls of the conductive pillar are angled with respect to a top-most surface of the epitaxial layer, a bottom surface of the conductive pillar is rounded, and a top-most surface of the conductive pillar is coplanar with the top-most surface of the epitaxial layer.

Claims20

Dependent claims

A super junction structure comprising:

a substrate, wherein the substrate has a first conductivity type;
an epitaxial layer over the substrate, wherein the epitaxial layer has a second conductivity type opposite the first conductivity type;
a bury layer between the epitaxial layer and the substrate, wherein the bury layer has the second conductivity type;
and
a conductive pillar in the epitaxial layer, wherein the conductive pillar has the first conductivity type, sidewalls of the conductive pillar are angled with respect to a top-most surface of the epitaxial layer, a bottom surface of the conductive pillar is rounded, and a top-most surface of the conductive pillar is coplanar with the top-most surface of the epitaxial layer.

2 more elements

Dependencies are inferred from the claim text.

Facts

Application

17/454,168Filed 9 Nov 2021

Priority

CN 201410614306.64 Nov 2014

Published

3 Mar 2022

Term ends

Not estimatedThe source records don’t support an estimate.

Classification15 codes

H10D 62/111
Reduced surface field [RESURF] PN junction structures: multiple RESURF structures, e.g. double RESURF or 3D-RESURF structures
H10D 30/0297
Of vertical dmos [vdmos] fets: using recessing of the gate electrodes, e.g. to form trench gate electrodes
H10D 30/663
Vertical dmos [vdmos] fets: having both source contacts and drain contacts on the same surface, i.e. up-drain VDMOS
H10D 30/668
Vertical dmos [vdmos] fets: having trench gate electrodes, e.g. UMOS transistors

Family

Application14/586,453Division · filed 30 Dec 2014

Application16/855,253Continuation · filed 22 Apr 2020

Application17/454,168Continuation

Application16/855,253Division

US 11,201,211 B2Related patent

US 12,040,358 B2Related patent

US 2016/0126307 A1Published application

US 2020/0251553 A1Published application

US 2022/0069074 A1This patent

From the US filing history. Foreign family members aren’t listed.

Method of manufacturing a super junction structure and super junction structure

Life of this patent

Method of manufacturing a super junction structure and super junction structure

Life of this patent

Abstract

Claims20