Back to results
US 2022/0069010 A1Published application
Memory array and method of forming thereof
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsI-CHE LEE, HUAI-YING HUANG
Life of this patent
Estimating the term…
Abstract
A memory array and a method for forming the memory array are disclosed. The memory array includes memory elements, selectors and conductive vias. Each selector includes two pairs of fin structures and a gate structure. The gate structure crosses the two pairs of fin structures. The conductive vias are electrically coupled to the two pairs of fin structures of the selectors.
Claims20
A memory array, comprising:
- a plurality of memory elements;
- a plurality of selectors configured to access the plurality of memory elements, wherein each of the plurality of selectors comprises:
- two pairs of fin structures extending in a first direction;
- and
- a gate structure extending in a second direction perpendicular to the first direction and crossing the two pairs of fin structures;
- and
- a plurality of first conductive vias electrically coupled to the two pairs of fin structures of the plurality of selectors,
- wherein the plurality of first conductive vias form a staggered pattern in the first direction.
5 more elements
A memory array, comprising:
- a plurality of memory elements;
- and
- a plurality of selectors configured to access the respective plurality of memory elements, wherein each of the plurality of selectors comprises:
- two pairs of fin structures extending in a first direction;
- and
- a gate structure extending in a second direction perpendicular to the first direction, crossing the two pairs of fin structures and defining two pairs of channel regions with the two pairs of fin structures;
- and
- a plurality of conductive vias arranged at corners of the plurality of selectors and electrically coupled to the two pairs of fin structures of the plurality of selectors.
5 more elements
A method for forming a memory array, comprising:
- providing a plurality of selectors, wherein the providing the plurality of selectors comprises:
- forming two pairs of fin structures extending in a first direction;
- and
- forming a gate structure extending in a second direction perpendicular to the first direction and crossing the two pairs of fin structures;
- providing a plurality of memory elements electrically coupled to the plurality of selectors;
- and
- providing a plurality of conductive vias electrically coupled to the two pairs of fin structures of the plurality of selectors, wherein the plurality of conductive vias are staggered.
4 more elements
Dependencies are inferred from the claim text.