Method for etching insulating layer, method for manufacturing display device using the same, and display device

A method for manufacturing a display device, the method comprising:

• forming a semiconductor layer on a substrate;
• forming a first gate insulating layer on the semiconductor layer;
• forming a first gate conductive layer on the first gate insulating layer;
• forming an amorphous silicon layer on the first gate insulating layer;
• forming a first interlayer insulating layer on the amorphous silicon layer;
• forming a second interlayer insulating layer on the first interlayer insulating layer;
• etching the second interlayer insulating layer, the first interlayer insulating layer, and the first gate insulating layer to form an opening;
• and
• forming a first data conductive layer on the second interlayer insulating layer, the first data conductive layer connecting to the semiconductor layer through the opening,
• wherein the forming of the opening comprises:
• applying a photoresist on the second interlayer insulating layer, and patterning the photoresist through a photo-process;
• first etching the second interlayer insulating layer and the first interlayer insulating layer until at least a portion of the amorphous silicon layer is exposed by utilizing the patterned photoresist as a mask;
• second etching the second interlayer insulating layer and the first interlayer insulating layer;
• third etching the amorphous silicon layer;
• and
• fourth etching the first gate insulating layer,
• wherein an etching gas utilized in the second etching comprises a material having a higher etching selection ratio of the first and second interlayer insulating layers to the amorphous silicon layer than an etching gas utilized in the first etching.

A display device comprising:

• a substrate;
• a semiconductor layer on the substrate;
• a first gate insulating layer on the semiconductor layer;
• a first gate conductive layer on the first gate insulating layer, the first gate conductive layer overlapping the semiconductor layer;
• a second gate insulating layer on the first gate conductive layer;
• a second gate conductive layer on the second gate insulating layer;
• a first interlayer insulating layer on the second gate conductive layer;
• a second interlayer insulating layer on the first interlayer insulating layer;
• an amorphous silicon layer between the first gate insulating layer and the first interlayer insulating layer;
• and
• a first data conductive layer on the second interlayer insulating layer, the first data conductive layer connecting to the semiconductor layer,
• wherein the first gate insulating layer, the second gate insulating layer, the first interlayer insulating layer, the second interlayer insulating layer, and the amorphous silicon layer include an opening overlapping the semiconductor layer, and
• wherein the first data conductive layer is connected to the semiconductor layer through the opening.