Method for improving size of contact holes of fdsoi device

A method for forming contact holes of an FDSOI device, comprising the following steps:

• step 1:
• providing a semiconductor structure comprising an NMOS area and a PMOS area, wherein the NMOS area comprises a first gate, a first source region and a first drain region, and wherein the PMOS area comprises a second gate, a second source region and a second drain region;
• wherein the semiconductor structure further comprises a silicon oxide layer disposed on the first and second gates, and the first and second source regions and the first and second drain regions;
• step 2:
• patterning a first source contact hole in the first source region and a first drain contact hole in the first drain region;
• patterning a second source contact hole in the second source region and a second drain contact hole in the second drain region;
• step 3:
• removing byproducts produced in the patterning of step 2;
• step 4:
• forming a first oxide film layer on the semiconductor structure, bottom surfaces and sidewalls of the first source contact hole, the second source contact hole, the first drain contact hole and the second drain contact hole;
• step 5:
• removing, by etching, the first oxide film layer from top surfaces of the semiconductor structure and from bottom surfaces of the first and second source contact holes and the first and second drain contact holes, while protecting the first oxide film layer from being removed from sidewalls of the first and second source contact holes and from the first and second drain contact holes;
• step 6:
• removing byproducts produced during etching the first oxide film layer in step 5;
• step 7:
• depositing a metal layer to fill the first and second source contact holes and the first and second drain contact holes, followed by planarization on the top surfaces of the semiconductor structure to adjust depths of the first and second source contact holes and the first and second drain contact holes;
• step 8:
• patterning a first gate contact hole in the first gate of the NMOS area and a second gate contact hole in the second gate of the PMOS area;
• step 9:
• removing byproducts produced during said gate contact holes in step 8 patterning;
• step 10:
• forming a second oxide film layer on the top surfaces of the semiconductor structure, bottom surfaces and sidewalls of the first and second gate contact holes;
• step 11:
• removing, by etching, the second oxide film layer from the top surfaces of the semiconductor structure and the bottom surfaces of the first gate contact hole and the second gate contact hole, while protecting the first oxide film layer from being removed from sidewalls of the first and second gate contact holes;
• step 12:
• removing byproducts produced in said etching the second oxide film layer in step 11;
• and
• step 13:
• depositing a metal layer to fill the first gate contact hole and the second gate contact hole, followed by planarization on the top surfaces of the semiconductor structure to adjust depths of the first and second gate contact holes.