Semiconductor memory device and manufacturing method of semiconductor memory device
AssigneeSK hynix Inc.
InventorNam Jae LEE
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Abstract
There are provided a semiconductor memory device and a manufacturing method of the semiconductor including: a plurality of source channels penetrating a source select line; a gate stack structure overlapping with the source select line; a connection pattern disposed between the source select line and the gate stack structure, the connection pattern being commonly connected to the plurality of source channels; and a plurality of vertical channels penetrating the gate stack structure, the plurality of vertical channels being commonly connected to the connection pattern.
Claims24
A semiconductor memory device comprising:
- a plurality of source channels penetrating a source select line;
- a gate stack structure overlapping with the source select line;
- a connection pattern disposed between the source select line and the gate stack structure, the connection pattern being commonly connected to the plurality of source channels;
- and
- a plurality of vertical channels penetrating the gate stack structure, the plurality of vertical channels being commonly connected to the connection pattern.
A semiconductor memory device comprising:
- a first source channel and a second source channel, extending in parallel to each other;
- a first source select line surrounding the first source channel;
- a second source select line surrounding the second source channel;
- a gate stack structure overlapping with the first source select line, the gate stack structure extending to overlap with the second source select line;
- a first vertical channel penetrating a first region of the gate stack structure that overlaps with the first source select line;
- a second vertical channel penetrating a second region of the gate stack structure that overlaps with the second source select line;
- a first connection pattern connecting the first source channel and the first vertical channel between the first source select line and the gate stack structure;
- a second connection pattern connecting the second source channel and the second vertical channel between the second source select line and the gate stack structure;
- and
- a source-side slit disposed between the first source select line and the second source select line, the source-side slit extending between the first connection pattern and the second connection pattern.
A semiconductor memory device comprising
- a plurality of source channels penetrating a source select line;
- a gate stack structure overlapping with the source select line;
- a plurality of vertical channels penetrating the gate stack structure;
- and
- a connection pattern disposed between the source select line and the gate stack structure to connect the plurality of vertical channels to the plurality of source channels, wherein a thickness of each vertical channel of the plurality of vertical channels is different from a thickness of each source channel of the plurality of source channels.
Dependencies are inferred from the claim text.