Semiconductor memory device and methods of manufacturing and operating the same
AssigneeSK hynix Inc.
InventorsDong Uk LEE, Hae Chang YANG
Life of this patent
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Abstract
A semiconductor memory device and methods of manufacturing and operating the same are set forth. The semiconductor memory device includes a stack structure including a plurality of interlayer insulating layers and a plurality of gate electrodes, which may be alternately stacked on a substrate, and a plurality of channel structures penetrating the stack structure in a vertical direction. Each of the plurality of channel structures includes a channel layer, a tunnel insulating layer, an emission preventing layer, and a charge storage layer, each of which vertically extends toward the substrate.
Claims20
A semiconductor memory device comprising:
- a stack structure including a plurality of interlayer insulating layers and a plurality of gate electrodes, which are alternately stacked on a substrate;
- and
- a plurality of channel structures penetrating the stack structure in a vertical direction,
- wherein each of the plurality of channel structures includes a channel layer, a tunnel insulating layer, an emission preventing layer, and a charge storage layer, which vertically extend toward the substrate.
A method of manufacturing a semiconductor memory device, the method comprising:
- forming a stack structure by alternately stacking a plurality of interlayer insulating layer and a plurality of sacrificial layers on a substrate;
- forming a plurality of holes penetrating the stack structure in a vertical direction;
- and
- sequentially forming a blocking insulating layer, a charge storage layer, an emission preventing layer, a tunnel insulating layer, and a channel layer on a sidewall of each of the plurality of holes.
A method of operating a semiconductor memory device, the method comprising:
- performing a program operation on a plurality of memory cells each including a channel layer, a tunnel insulating layer, an emission preventing layer, a charge storage layer, a blocking insulating layer, and a compensation charge storage layer in response to a program command;
- suspending the program operation in response to a suspend command received from outside of the semiconductor memory device, and applying a positive voltage to bit lines or a source line, connected to the memory cells, during a suspend period;
- and
- re-performing the suspended program operation in response to a resume command received from outside of the semiconductor memory device.
Dependencies are inferred from the claim text.