Semiconductor storage device
AssigneeSocionext Inc.
InventorYasumitsu SAKAI
Life of this patent
Estimating the term…
Abstract
A ROM cell includes first and second three-dimensional transistors. The second transistor is formed above the first transistor, and the channel portions of the first and second transistors overlap each other. First data is stored depending on whether first and second local interconnects connected to the nodes of the first transistor are connected to a same line, or different lines, out of a bit line and a ground power supply line. Second data is stored depending on whether third and fourth local interconnects connected to the nodes of the second transistor are connected to a same line, or different lines, out of a bit line and a ground power supply line.
Claims11
A semiconductor storage device provided with a read only memory (ROM) cell, comprising:
- a word line extending in a first direction;
- first and second bit lines extending in a second direction perpendicular to the first direction;
- and
- a ground power supply line extending in the second direction,
- wherein
- the ROM cell includes
- a first transistor that is a three-dimensional transistor provided between the first bit line and the ground power supply line,
- a second transistor that is a three-dimensional transistor provided between the second bit line and the ground power supply line, formed above the first transistor, channel portions of the first and second transistors overlapping each other as viewed in plan,
- a first local interconnect connected to a source of the first transistor and connected to the first bit line or the ground power supply line,
- a second local interconnect connected to a drain of the first transistor and connected to the first bit line or the ground power supply line,
- a third local interconnect connected to a source of the second transistor and connected to the second bit line or the ground power supply line, and
- a fourth local interconnect connected to a drain of the second transistor and connected to the second bit line or the ground power supply line,
- gates of the first and second transistors are connected to the word line, and
- first data is stored in the ROM cell depending on whether the first and second local interconnects are connected to a same line, or different lines, out of the first bit line and the ground power supply line, and second data is stored in the ROM cell depending on whether the third and fourth local interconnects are connected to a same line, or different lines, out of the second bit line and the ground power supply line.
A semiconductor storage device provided with a read only memory (ROM) cell, comprising:
- a word line extending in a first direction;
- a bit line extending in a second direction perpendicular to the first direction;
- and
- a ground power supply line extending in the second direction,
- wherein
- the ROM cell includes
- a first transistor that is a three-dimensional transistor provided between the bit line and the ground power supply line,
- a second transistor that is a three-dimensional transistor provided between the bit line and the ground power supply line, formed above the first transistor, channel portions of the first and second transistors overlapping each other as viewed in plan,
- a first local interconnect connected to a source of the first transistor,
- a second local interconnect connected to a source of the second transistor,
- a third local interconnect connected to a drain of the first transistor, and
- a fourth local interconnect connected to a drain of the second transistor,
- gates of the first and second transistors are connected to the word line,
- the first and second local interconnects are mutually connected and also connected with the bit line or the ground power supply line,
- the third and fourth local interconnects are mutually connected and also connected with the bit line or the ground power supply line, and
- data is stored in the ROM cell depending on whether the paired first and second local interconnects and the paired third and fourth local interconnects are connected to a same line, or different lines, out of the bit line and the ground power supply line.
Dependencies are inferred from the claim text.