Gate dielectric repair on three-node access device formation for vertical three-dimensional (3d) memory

A method for forming arrays of vertically stacked memory cells, having horizontally oriented access devices and vertically oriented access lines, comprising:

• depositing alternating layers of a dielectric material and a sacrificial material to form a vertical stack;
• forming a plurality of first vertical openings, having a first horizontal direction and a second horizontal direction, through the vertical stack and extending predominantly in the second horizontal direction to form elongated vertical pillar columns with sidewalls in the vertical stack;
• conformally depositing a gate dielectric in the plurality of first vertical openings;
• forming a conductive material on the gate dielectric;
• removing portions of the conductive material to form a plurality of separate, vertical access lines;
• repairing a first side of the gate dielectric exposed where the conductive material was removed;
• forming a second vertical opening through the vertical stack and extending predominantly in the first horizontal direction to expose sidewalls adjacent a first region of the sacrificial material;
• selectively removing the sacrificial material in the first region a first horizontal distance from the second vertical openings to form first horizontal openings;
• repairing a second side of the gate dielectric exposed where the sacrificial material was removed in the first region;
• and
• sequentially depositing a first source/drain region, a channel region, and a second source/drain region in the first horizontal opening to form a horizontally oriented three-node access device.

A method for forming arrays of vertically stacked memory cells, having horizontally oriented access devices and vertically oriented access lines, comprising:

• depositing alternating layers of a dielectric material and a sacrificial material to form a vertical stack
• forming a plurality of first vertical openings, having a first horizontal direction and a second horizontal direction, through the vertical stack and extending predominantly in the second horizontal direction to form elongated vertical, pillar columns with sidewalls in the vertical stack;
• conformally depositing a gate dielectric material in the plurality of first vertical openings;
• forming a conductive material on the gate dielectric;
• removing portions of the conductive material to form a plurality of separate, vertical access lines along the sidewalls of the elongated vertical, pillar columns;
• repairing a first side of the gate dielectric material exposed where the conductive material was removed;
• forming a second vertical opening through the vertical stack and extending predominantly in the first horizontal direction to expose sidewalls adjacent a first region of the sacrificial material;
• selectively removing the sacrificial material in the first region a first horizontal distance from the second vertical openings to form first horizontal openings to a first electrode in a second region of the vertical stack;
• repairing a second side of the gate dielectric exposed where the sacrificial material was removed in the first region;
• repairing a surface of the first electrode in the second region;
• and
• depositing a first source/drain region, a channel region, and a second source/drain region in the first horizontal openings.