Three-dimensional nanoribbon-based dynamic random-access memory

A memory device, comprising:

• a support structure;
• a nanoribbon over the support structure;
• a gate stack, at least partially surrounding a portion of the nanoribbon;
• and
• a capacitor that includes a first capacitor electrode, a second capacitor electrode, and a capacitor insulator between the first and second capacitor electrodes,
• wherein:
• each of the first capacitor electrode, the second capacitor electrode, and the capacitor insulator at least partially surrounds a further portion of the nanoribbon,
• the first capacitor electrode is closer to the gate stack than each of the second capacitor electrode and the capacitor insulator, and
• the capacitor insulator is closer to the gate stack than the second capacitor electrode.

A memory device, comprising:

• a storage node;
• and
• a transistor that includes:
• a nanoribbon of a semiconductor material,
• a first source or drain (S/D) region, coupled to a bitline (BL),
• a second (S/D) region, coupled to the storage node, and
• a gate stack that at least partially surrounds a portion of the nanoribbon between the first S/D region and the second S/D region.