Channel formation for vertical three dimensional (3d) memory

A method for forming arrays of vertically stacked memory cells, having horizontally oriented access devices and vertically oriented access lines, comprising:

• depositing alternating layers of a dielectric material and a yttrium oxide (Y2O3) material in repeating iterations to form a vertical stack;
• forming a plurality of vertical openings, having a first horizontal direction and a second horizontal direction, through the vertical stack and extending predominantly in the second horizontal direction, to form elongated vertical, pillar columns with sidewalls in the vertical stack;
• patterning the elongated vertical, pillar columns to expose locations to form channel regions in the layers of the yttrium oxide (Y2O3) material;
• selectively etching to remove portions of the yttrium oxide (Y2O3) material in the first horizontal direction to form first horizontal openings in opposing sides of sidewalls of the elongated vertical, pillar columns;
• and
• depositing a channel material in the first horizontal openings to form channel regions on the opposing sides of the sidewalls of the elongated vertical, pillar columns.

A method for forming arrays of vertically stacked memory cells, having horizontally oriented access devices and vertically oriented access lines, comprising:

• depositing alternating layers of a dielectric material and a semiconductor material to form a vertical stack;
• forming a plurality of vertical openings, having a first horizontal direction and a second horizontal direction, through the vertical stack and extending predominantly in the second horizontal direction, to form elongated vertical, pillar columns with sidewalls in the vertical stack;
• patterning the elongated vertical, pillar columns to expose a location to form channel regions in semiconductor material;
• selectively etching to remove portions of the semiconductor material in the first horizontal direction to form first horizontal openings on opposite sidewalls of the elongated vertical, pillar columns against the semiconductor material;
• selectively depositing a channel material in the first horizontal openings to form channel regions of the horizontally oriented access devices;
• conformally depositing a conductive material on a gate dielectric material in the plurality of vertical openings;
• and
• removing portions of the first conductive material to form a plurality of separate, vertical access lines along the sidewalls of the elongated vertical, pillar columns opposing the channel regions.

A memory cell array, comprising:

• a plurality of access transistors stacked on one another, each of the access transistors including a first source/drain region, a second source/drain region, and a channel region therebetween which are horizontally arranged, and a body region, wherein the channel region includes a channel material and a passivation material;
• at least one access line elongating vertically and coupled to each of the channel regions of the plurality of access transistors with an intervention of a gate dielectric;
• a plurality of storage capacitors stacked on one another, each of the plurality of storage capacitors lying horizontally and coupled to a corresponding one of the second source/drain regions of the plurality of access transistors;
• and
• a plurality of digit lines, each of the plurality of digit lines coupled to a corresponding one of the first source/drain regions of the plurality of access transistors.