Semiconductor device and method of fabricating the same

A semiconductor device, comprising:

• a substrate that includes a peripheral region and a logic cell region;
• a device isolation layer that defines a first active pattern on the peripheral region, a second active pattern on the logic cell region, and a third active pattern on the logic cell region;
• first, second, and third transistors on the first, second, and third active patterns, respectively;
• an interlayer dielectric layer that covers the first, second, and third transistors;
• and
• a plurality of active contacts and a gate contact that penetrate at least a portion of the interlayer dielectric layer and are correspondingly connected to the first, second, and third transistors,
• wherein each of the first, second, and third transistors includes:
• a gate dielectric layer on a corresponding pattern of the first, second, and third active patterns;
• a gate electrode on the gate dielectric layer and electrically connected to the gate contact;
• a gate spacer that covers a sidewall of the gate electrode;
• a pair of source/drain patterns in an upper portion of a corresponding one of the first, second, and third active patterns and on both sides of the gate electrode, the pair of source/drain patterns being electrically connected to the active contacts;
• and
• a high-k dielectric layer between the gate electrode and the gate dielectric layer and between the gate electrode and the gate spacer,
• wherein a thickness of the gate dielectric layer in the first transistor is greater than a thickness of the gate dielectric layer in each of the second and third transistors,
• wherein the second active pattern includes a semiconductor pattern in an upper portion of the second active pattern, wherein the semiconductor pattern overlaps the gate electrode,
• wherein at least a portion of a top surface of the device isolation layer is located at a higher level than a top surface of the second active pattern and a top surface of the third active pattern, and
• wherein a profile of the top surface of the device isolation layer includes two or more concave portions between the second active pattern and the third active pattern.

A method of fabricating a semiconductor device, the method comprising:

• preparing a substrate that includes a peripheral region and a logic cell region;
• patterning the substrate wherein a trench is formed that defines a first active pattern on the peripheral region, a second active pattern on the logic cell region, and a third active pattern on the logic cell region;
• filling the trench with a device isolation layer;
• forming a dielectric layer that covers the device isolation layer and the first, second, and third active patterns;
• performing a first etching using a first photoresist pattern that removes a portion of the second active pattern and a portion of the dielectric layer on the second active pattern, wherein the first photoresist pattern has a first opening that exposes the second active pattern;
• forming a semiconductor pattern on the second active pattern;
• and
• performing a second etching using a second photoresist pattern that removes a remaining portion of the dielectric layer on the third active pattern, wherein the second photoresist pattern has a second opening that exposes the second and third active patterns,
• wherein, between the second active pattern and the third active pattern, a profile of a top surface of the device isolation layer has two or more concave portions.