US 2022/0068903 A1 · THREE-DIMENSIONAL MEMORY DEVICE WITH VERTICAL FIELD EFFECT TRANSISTORS AND METHOD OF MAKING THEREOF

Abstract

A semiconductor structure includes at least one set of vertical field effect transistors embedded within dielectric material layers overlying a substrate. Each vertical field effect transistor includes a bottom doped semiconductor electrode, a vertical transistor channel, a cylindrical gate dielectric, and a top doped semiconductor electrode. A three-dimensional NAND memory array can be provided over the first field effect transistors, and can be electrically connected to the vertical field effect transistors via metal interconnect structures. Alternatively, a three-dimensional NAND memory array can be formed on another substrate, which can be bonded to the substrate via metal-to-metal bonding. The vertical field effect transistors can be employed as switches for bit lines, word lines, or other components of the three-dimensional NAND memory array.

Claims20

Dependent claims

A semiconductor structure comprising:

at least one set of vertical field effect transistors located above, and vertically spaced from, a semiconductor substrate, wherein each vertical field effect transistor within each set of vertical field effect transistors comprises a bottom doped semiconductor electrode, a vertical transistor channel, a gate dielectric which surrounds the vertical transistor channel, and a top doped semiconductor electrode;
and
a three-dimensional NAND memory array located over the at least one set of vertical field effect transistors, wherein electrical nodes of the three-dimensional NAND memory array are electrically connected to a respective one of the at least one set of vertical field effect transistors.

A method of forming a semiconductor structure, comprising:

forming bottom doped semiconductor electrodes over first dielectric material layers that overlie a semiconductor substrate;
forming a gate electrode including a plurality of vertically-extending openings over the bottom doped semiconductor electrodes wherein the bottom doped semiconductor electrodes are exposed underneath the vertically-extending openings;
forming a combination of a cylindrical gate dielectric and a vertical transistor channel within each of the vertically-extending openings;
forming top doped semiconductor electrodes on the vertical transistor channels;
forming second dielectric material layers over the top doped semiconductor electrodes;
and
forming a three-dimensional NAND memory array over the second dielectric material layers, wherein electrical nodes of the three-dimensional NAND memory array are electrically connected to a respective one of the top doped semiconductor electrodes.

4 more elements

Dependencies are inferred from the claim text.

Three-dimensional memory device with vertical field effect transistors and method of making thereof

Life of this patent

Three-dimensional memory device with vertical field effect transistors and method of making thereof

Life of this patent

Abstract

Claims20