Semiconductor package including a redistribution structure
AssigneeSamsung Electronics Co., Ltd.
InventorYONGHWAN KWON
Life of this patent
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Abstract
A semiconductor package includes: a first wiring pattern; a dielectric layer that covers the first wiring pattern; a second wiring pattern on the dielectric layer, wherein the second wiring pattern includes a line part that extends in a first direction and a via part that connects the line part to the first wiring pattern; a pad pattern electrically connected to the second wiring pattern, wherein the pad pattern includes a connection part and an extension part, wherein the connection part covers a first surface of the line part of the second wiring pattern, and the extension part has a top surface at a level lower than a level of the top surface of the line part of the second wiring pattern; and a seed pattern between the extension part and the dielectric layer.
Claims20
A semiconductor package, comprising:
- a first wiring pattern;
- a dielectric layer that covers the first wiring pattern;
- a second wiring pattern on the dielectric layer, wherein the second wiring pattern includes a line part that extends in a first direction and a via part that connects the line part to the first wiring pattern;
- a pad pattern electrically connected to the second wiring pattern, wherein the pad pattern includes a connection part and an extension part, wherein the connection part covers a first surface of the line part of the second wiring pattern, and the extension part has a top surface at a level lower than a level of the top surface of the line part of the second wiring pattern;
- and
- a seed pattern between the extension part and the dielectric layer.
A semiconductor package, comprising:
- a lower redistribution structure;
- a first semiconductor chip on the lower redistribution structure;
- a dielectric layer on the first semiconductor chip;
- a first wiring pattern in the dielectric layer,
- a second wiring pattern on the dielectric layer, wherein the second wiring pattern includes a line part that extends in a first direction and a via part that connects the line part to the first wiring pattern;
- a pad pattern electrically connected to the second wiring pattern, wherein the pad pattern includes a connection part and an extension part, wherein the connection part covers a top surface of the line part of the second wiring pattern, and the extension part has a top surface at a level lower than a level of the top surface of the line part of the second wiring pattern;
- a passivation pattern that covers the second wiring pattern and the connection part of the pad pattern, wherein the passivation pattern has a pad opening that exposes at least a portion the extension part of the pad pattern;
- a seed pattern between the pad pattern and the dielectric layer;
- a connection terminal in the pad opening overlapping the extension part of the pad pattern;
- and
- a second semiconductor chip on the connection terminal and electrically connected to the lower redistribution structure through the connection terminal.
A semiconductor package, comprising:
- a first wiring pattern;
- a dielectric layer that covers the first wiring pattern;
- a second wiring pattern on the dielectric layer, wherein the second wiring pattern including a line part that extends in a first direction and a via part that connects the line part to the first wiring pattern;
- and
- a pad pattern electrically connected to the second wiring pattern, wherein the pad pattern includes an extension part and a connection part, wherein the extension part has a width greater than a width of the line part, and the connection part connects the extension part to the line part,
- wherein the connection part covers a top surface and a lateral surface of the line part of the second wiring pattern.
Dependencies are inferred from the claim text.