Hybrid memory structure
AssigneePowerchip Semiconductor Manufacturing Corporation
InventorsChen-Liang Ma, Zih-Song Wang
Life of this patent
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Abstract
A hybrid memory structure including a substrate, a flash memory, a first resistive random access memory (RRAM), and a second RRAM is provided. The flash memory is located on the substrate. The flash memory includes a gate, a first doped region, and a second doped region. The gate is located on the substrate. The first doped region is located in the substrate on one side of the gate. The second doped region is located in the substrate on another side of the gate. The first RRAM is electrically connected to one of the gate, the first doped region, and the second doped region. The second RRAM is electrically connected to another of the gate, the first doped region, and the second doped region.
Claims20
A hybrid memory structure, comprising:
- a substrate;
- a flash memory located on the substrate and comprising:
- a gate located on the substrate;
- a first doped region located in the substrate on one side of the gate;
- and
- a second doped region located in the substrate on another side of the gate;
- a first resistive random access memory (RRAM) electrically connected to one of the gate, the first doped region, and the second doped region;
- and
- a second RRAM electrically connected to another of the gate, the first doped region, and the second doped region.
Dependencies are inferred from the claim text.