Three-dimensional semiconductor memory device

A three-dimensional semiconductor memory device comprising:

• a first substrate including a bit-line connection region, a word-line connection region, and a first peripheral region;
• a cell array structure including a memory cell array, which includes memory cells three-dimensionally arranged on the bit-line connection region and the word-line connection region of the first substrate, and the cell array structure including lower control circuits, which are provided on the first peripheral region of the first substrate;
• a second substrate including a first core region, a second core region, and a second peripheral region, which are overlapped with the bit-line connection region, the word-line connection region, and the first peripheral region, respectively;
• and
• a peripheral circuit structure including sense amplifiers provided on the first core region of the second substrate, sub-word line drivers provided on the second core region of the second substrate, and upper control circuits provided on the second peripheral region of the second substrate.

A three-dimensional semiconductor memory device comprising:

• a first substrate including a bit-line connection region, a word-line connection region, and a first peripheral region;
• a cell array structure on the first substrate, the cell array structure comprising:
• bit lines, which are extended in a first direction perpendicular to a top surface of the first substrate,
• word lines, which are extended in a second direction to cross the bit lines,
• memory cells, which are provided at intersections of the bit lines and the word lines,
• first lower metal pads, which are provided on the bit-line connection region and are connected to the bit lines,
• second lower metal pads, which are provided on the word-line connection region and are connected to the word lines, and
• third lower metal pads, which are provided on the first peripheral region and are connected to lower control circuits;
• a second substrate including a first core region, a second core region, and a second peripheral region, which are overlapped with the bit-line connection region, the word-line connection region, and the first peripheral region, respectively;
• and
• a peripheral circuit structure on the second substrate, the peripheral circuit structure comprising:
• first upper metal pads provided on the first core region and connected to sense amplifiers,
• second upper metal pads provided on the second core region and connected to sub-word line drivers, and
• third upper metal pads provided on the second peripheral region and connected to upper control circuits,
• wherein the first lower metal pads are bonded to the first upper metal pads,
• the second lower metal pads are bonded to the second upper metal pads, and
• the third lower metal pads are bonded to the third upper metal pads.