Semiconductor package

A semiconductor package, comprising:

• a substrate including a chip region;
• a semiconductor chip on the chip region of the substrate;
• a mold layer on the substrate and covering the semiconductor chip;
• a shield layer on the mold layer and covering a top surface and a side surface of the mold layer and a side surface of the substrate, the shield layer extending onto a bottom surface of the substrate and including an opening region on the bottom surface of the substrate;
• and
• a ground terminal on the bottom surface of the substrate and electrically connected to the shield layer,
• wherein the ground terminal is on the chip region.

A semiconductor package, comprising:

• a substrate including at least one ground pad, a ground pattern, and a ground terminal pad;
• a semiconductor chip on the substrate;
• a mold layer on the substrate and covering the semiconductor chip;
• a shield layer on the mold layer and covering a top surface and a side surface of the mold layer and a side surface of the substrate, the shield layer extending onto a bottom surface of the substrate and including a plurality of opening regions on the bottom surface of the substrate;
• a plurality of test pads at the bottom surface of the substrate;
• an outer terminal on the bottom surface of the substrate;
• and
• a ground terminal on the bottom surface of the substrate,
• wherein:
• a bottom surface of the at least one ground pad is at the bottom surface of the substrate,
• a side surface of the ground pattern is at the side surface of the substrate,
• the shield layer on the bottom surface of the substrate is in contact with the bottom surface of the at least one ground pad and the side surface of the ground pattern, and
• the test pad, the ground terminal, and the outer terminal are aligned with the plurality of opening regions of the shield layer such that the plurality of opening regions of the shield layer expose the test pad, the ground terminal, and the outer terminal.