Semiconductor package

A semiconductor package comprising:

• a redistribution substrate comprising a first redistribution layer;
• a core structure on the redistribution substrate and comprising a first through-hole and at least one second through-hole adjacent a periphery of the first through-hole;
• a semiconductor chip in the first through-hole of the core structure and electrically connected to the first redistribution layer;
• at least one vertical connection structure in the at least one second through-hole of the core structure and electrically connected to the first redistribution layer;
• an encapsulant on the redistribution substrate, the semiconductor chip, the core structure, and the at least one vertical connection structure;
• and
• a redistribution structure on the encapsulant and comprising a second redistribution layer electrically connected to the at least one vertical connection structure,
• wherein the at least one vertical connection structure comprises a metal pillar extending in a vertical direction and a first plating layer on a surface of the metal pillar,
• the core structure comprises a metal frame adjacent a periphery of the semiconductor chip and the at least one vertical connection structure, and a second plating layer on a surface of the metal frame, and
• each of the first and second plating layers comprises a respective roughened surface.

A semiconductor package comprising:

• a redistribution substrate comprising a redistribution layer;
• a semiconductor chip on the redistribution substrate and electrically connected to the redistribution layer;
• a vertical connection structure on the redistribution substrate, electrically connected to the redistribution layer, and having a surface roughness (Ra) of about 0.5 μm or more;
• and
• an encapsulant on the redistribution substrate, the semiconductor chip, and the vertical connection structure.