Semiconductor device

A semiconductor device, comprising:

• a transistor on a substrate;
• an interlayer insulating layer on the transistor;
• a first metal-containing layer on the interlayer insulating layer, the first metal-containing layer including a lower interconnection line;
• and
• a second metal-containing layer on the first metal-containing layer,
• wherein:
• the second metal-containing layer includes a resistor metal layer and an upper interconnection line on the resistor metal layer,
• the resistor metal layer is between the upper interconnection line and the lower interconnection line,
• the upper interconnection line includes:
• a first portion vertically overlapped with the resistor metal layer, and
• a second portion horizontally offset from the resistor metal layer, and
• a bottom surface of the first portion of the upper interconnection line is located at a level higher than a bottom surface of the second portion of the upper interconnection line.

A semiconductor device, comprising:

• a substrate including an active region;
• a device isolation layer defining active patterns on the active region, the device isolation layer covering a lower side surface of each of the active patterns, an upper portion of each of the active patterns protruding above the device isolation layer;
• a pair of source/drain patterns in the upper portion of each of the active patterns;
• a channel pattern between the pair of source/drain patterns;
• a gate electrode crossing the channel pattern and extending in a first direction;
• gate spacers at both sides of the gate electrode and extending in the first direction, along with the gate electrode;
• a gate dielectric pattern between the gate electrode and the channel pattern and between the gate electrode and the gate spacer;
• a gate capping pattern on a top surface of the gate electrode and extending in the first direction, along with the gate electrode;
• a first interlayer insulating layer on the gate capping pattern;
• an active contact penetrating the first interlayer insulating layer and being coupled to at least one of the source/drain patterns;
• a gate contact penetrating the first interlayer insulating layer and being coupled to the gate electrode;
• a first metal-containing layer in a second interlayer insulating layer on the first interlayer insulating layer;
• and
• a second metal-containing layer in a third interlayer insulating layer on the second interlayer insulating layer,
• wherein:
• the first metal-containing layer includes a lower interconnection line,
• the second metal-containing layer includes:
• a resistor on the first metal-containing layer;
• an upper interconnection line on the resistor;
• and
• a first via below the upper interconnection line and connected to the resistor,
• the resistor includes:
• a first insulating layer;
• a resistor metal layer on the first insulating layer;
• and
• a second insulating layer on the resistor metal layer, and
• the resistor metal layer includes a recessed side surface.