Metal line and via barrier layers, and via profiles, for advanced integrated circuit structure fabrication

A method of fabricating an integrated circuit structure, the method comprising:

• forming a partial trench in an inter-layer dielectric (ILD layer, the ILD layer on an etch stop layer;
• etching a hanging via that lands on the etch stop layer;
• and
• performing a breakthrough etch through the etch stop layer to form a trench and via opening in the ILD layer and the etch stop layer.

A computing device, comprising:

• a board;
• and
• a component coupled to the board, the component including an integrated circuit structure, comprising:
• a first conductive interconnect line in a first inter-layer dielectric (ILD) layer above a substrate;
• a second conductive interconnect line in a second ILD layer above the first ILD layer;
• and
• a conductive via coupling the first conductive interconnect line and the second conductive interconnect line, the conductive via having a single, nitrogen-free tantalum (Ta) barrier layer.

A computing device, comprising:

• a board;
• and
• a component coupled to the board, the component including an integrated circuit structure, the integrated circuit structure fabricated according to a method comprising:
• forming a partial trench in an inter-layer dielectric (ILD layer, the ILD layer on an etch stop layer;
• etching a hanging via that lands on the etch stop layer;
• performing a breakthrough etch through the etch stop layer to form a trench and via opening in the ILD layer and the etch stop layer.