Capacitor in a three-dimensional memory structure

A memory device comprising:

• a memory array extending over a substrate, the memory array including multiple vertically arranged tiers comprising memory cells;
• a first region under the memory array including control circuitry for the memory array;
• a second region adjacent the first region under the memory array and outside a horizontal extent of the memory array, the second region having pads to couple to the control circuitry;
• a third region adjacent the memory array and disposed above the second region, the third region including:
• dielectric material;
• and
• conductive structures extending vertically in the dielectric material and alongside at least a portion of the memory array, the conductive structures separated by dielectric material and arranged to form a capacitor;
• and
• nodes coupled to the conductive structures such that the nodes are configured to operatively provide different voltages to selected ones of the conductive structures.

A method of forming a memory device, the method comprising:

• forming a first region, in a substrate, including control circuitry for a memory array;
• forming the memory array over the first region, including forming the memory array having multiple vertically arranged tiers comprising memory cells;
• forming a second region adjacent the memory array and disposed above the first region, including forming dielectric material in the second region;
• forming conductive structures extending vertically in the dielectric material and alongside at least a portion of the memory array, with the conductive structures separated by portions of the dielectric material;
• and
• coupling nodes to the conductive structures such that the conductive structures and the dielectric material form a capacitor.