Interconnection structure and semiconductor package including the same

An interconnection structure, comprising:

• a first dielectric layer including an opening, wherein the opening has a lower part and an upper part, the upper part having a horizontal width greater than a horizontal width of the lower part;
• a first interconnection pattern in the opening;
• a barrier layer between the first dielectric layer and the first interconnection pattern;
• a passivation layer that covers a top surface of the first interconnection pattern;
• a second dielectric layer on the first dielectric layer and the passivation layer;
• a second interconnection pattern that penetrates the second dielectric layer and is electrically coupled to the first interconnection pattern;
• and
• an external terminal below the first dielectric layer, the external terminal electrically connected to the first interconnection pattern,
• wherein the barrier layer includes:
• a first barrier layer in the lower part of the opening;
• and
• a second barrier layer in the upper part of the opening.

A semiconductor package, comprising:

• a redistribution substrate that includes at least one redistribution layer;
• a semiconductor chip mounted on the redistribution substrate;
• a plurality of chip pads on one surface of the semiconductor chip, the one surface being directed toward the redistribution substrate;
• a plurality of substrate pads on a top surface of the redistribution substrate, the top surface being directed toward the semiconductor chip;
• a plurality of external terminals on a bottom surface of the redistribution substrate;
• and
• a molding member on the top surface of the redistribution substrate, the molding member covering the semiconductor chip,
• wherein the redistribution layer includes:
• a dielectric layer;
• an interconnection pattern that includes a head part exposed with respect to a top surface of the dielectric layer and a tail part connected to the head part, the tail part extending from the head part to a bottom surface of the dielectric layer;
• a first barrier layer between the dielectric layer and the interconnection pattern;
• a second barrier layer on the first barrier layer and between the dielectric layer and the head part of the interconnection pattern;
• and
• a passivation layer that covers a top surface of the dielectric layer and a top surface of the interconnection pattern,
• wherein the top surface of the dielectric layer, the top surface of the interconnection pattern, and a top surface of the second barrier layer are coplanar.