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AssigneeIntel Corporation
InventorsCharles H. WALLACE, Marvin Y. PAIK, Hyunsoo PARK, Mohit K. HARAN, Alexander F. KAPLAN, Ruth A. BRAIN
Estimating the term…
Methods and architectures for IC interconnect trenches, and trench plugs that define separations between two adjacent trench ends. Plugs and trenches may be defined through a multiple patterning process. An upper grating pattern may be summed with a plug keep pattern into a pattern accumulation layer. The pattern accumulation layer may be employed to define plug masks. A lower grating pattern may then be summed with the plug masks to define a pattern in a trench ILD material, which can then be backfilled with interconnect metallization. As such, a complex damascene interconnect structure can be fabricated at the scaled-down geometries achievable with pitch-splitting techniques. In some embodiments, the trenches are located at spaces between first spacer masks defined in a patterning process associated with the first grating pattern while the plug masks are located based on a tone-inversion of second spacer masks associated with the second grating pattern.
An integrated circuit (IC), comprising:
A system, comprising:
A mask stack for formation of ends of conductive traces in an interconnect level of an integrated circuit (IC), the mask stack comprising:
Dependencies are inferred from the claim text.