Back to results
US 2022/0068706 A1Published application
Method of manufacturing semiconductor device
AssigneeRenesas Electronics Corporation
InventorsHitoshi MAEDA, Tatsuyoshi MIHARA, Hiroki SHINKAWATA
Life of this patent
Estimating the term…
Abstract
Gate patterns are formed on a semiconductor layer and a conductive film is formed on the semiconductor layer so as to cover the gate patterns. By performing a polishing process to the conductive film and patterning the polished conductive film, pad layers are formed between the gate patterns via sidewall spacers.
Claims18
A method of manufacturing a semiconductor device, comprising steps of:
- (a) providing an SOI substrate having a semiconductor substrate, an insulating layer formed on the semiconductor substrate, and a semiconductor layer formed on the insulating layer;
- (b) after the a) forming a first conductive film on the semiconductor layer;
- (c) after the (b), forming a first insulating film on the first conductive film;
- (d) after the (c), patterning the first conductive film and the first insulating film, thereby forming a gate pattern and a cap film;
- (e) after the (d), implanting an impurity into the semiconductor layer located on both sides of the gate pattern, thereby forming a first impurity region;
- (f) after the (e), forming a first sidewall spacer made of a second insulating film on a side surface of the gate pattern;
- (g) after the (f), forming a second conductive film on the first impurity region so as to cover the gate pattern, the cap film, and the first sidewall spacer;
- (h) after the (g), performing a polishing process to the second conductive film until the cap film is exposed;
- (i) after the (h), patterning a part of the second conductive film, thereby forming a pad layer made of the remaining second conductive film;
- and
- (j) after the (i), filling a portion, from where the second conductive film has been removed, with a third insulating film.
8 more elements
A method of manufacturing a semiconductor device, comprising steps of:
- (a) forming a first conductive film on a semiconductor substrate;
- (b) after the (a), forming a first insulating film on the first conductive film;
- (c) after the (b), patterning the first conductive film and the first insulating film, thereby forming a gate pattern and a cap film;
- (d) after the (c), implanting an impurity into the semiconductor substrate located on both sides of the gate pattern, thereby forming a first impurity region;
- (e) after the (d) forming a first sidewall spacer made of a second insulating film on a side surface of the gate pattern;
- f after the (e), forming a second conductive film on the first impurity region so as to cover the gate pattern, the cap film, and the first sidewall spacer;
- (g) after the (f), performing a polishing process to the second conductive film until the cap film is exposed;
- (h) after the (g), patterning a part of the second conductive film, thereby forming a pad layer;
- and
- (i) after the (h), filling a portion from where the second conductive film has been removed, with a third insulating film.
7 more elements
Dependencies are inferred from the claim text.