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US 2022/0068660 A1Published application
Dishing prevention structure embedded in a gate electrode
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorTa-Wei Lin
Life of this patent
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Abstract
Various embodiments of the present disclosure are directed towards a semiconductor device. The semiconductor device includes a semiconductor substrate. A gate dielectric is disposed over the semiconductor substrate. A first source/drain region and a second source/drain region are disposed in the semiconductor substrate and on opposite sides of the gate dielectric. A gate electrode is disposed over the gate dielectric. A first dishing prevention structure is embedded in the gate electrode, where a perimeter of the first dishing prevention structure is disposed within a perimeter of the gate electrode.
Claims20
A method, the method comprising:
- forming a first dielectric layer over a semiconductor substrate;
- forming a first opening in the first dielectric layer and over a gate dielectric structure, wherein the first opening at least partially overlies the gate dielectric structure;
- forming a conductive layer over the gate dielectric structure and in the first opening;
- forming a plurality of second openings in the conductive layer and vertically spaced from the gate dielectric structure, wherein a perimeter of the gate dielectric structure laterally surrounds the plurality of second openings;
- forming a dishing prevention layer on the conductive layer and in the plurality of second opening;
- and
- performing a planarization process on the dishing prevention layer and the conductive layer.
4 more elements
A method, the method comprising:
- depositing an interlayer dielectric (ILD) layer over a semiconductor substrate;
- forming a first opening in the ILD layer and overlying a gate dielectric structure;
- depositing a gate electrode material layer over the gate dielectric structure and in the first opening, wherein the gate electrode material layer is formed with an upper surface that is disposed over an upper surface of the ILD layer and that extends continuously from a first side of the first opening to a second side of the first opening opposite the first side;
- forming a second opening in the gate electrode material layer and vertically spaced from the gate dielectric structure, wherein forming the second opening comprises removing a portion of the gate electrode material layer that overlies the gate dielectric structure;
- forming a dishing prevention layer on the gate electrode material layer and in the second opening;
- and
- performing a planarization process on the dishing prevention layer and the gate electrode material layer.
4 more elements
A method, the method comprising:
- forming a first dielectric layer over a semiconductor substrate;
- forming a first opening in the first dielectric layer and overlying a first gate dielectric structure, wherein forming the first opening comprises removing a first dummy gate electrode structure;
- forming a second opening in the first dielectric layer and overlying a second gate dielectric structure, wherein forming the second opening comprises removing a second dummy gate electrode structure, and wherein the second opening is laterally spaced from the first opening;
- depositing a conductive layer over both the first gate dielectric structure and the second gate dielectric structure and in both the first opening and the second opening, wherein the conductive layer is formed with an upper surface that is disposed over an upper surface of the first dielectric layer, and wherein the upper surface of the conductive layer extends laterally over both the first opening and the second opening;
- forming a patterned masking layer over the upper surface of the conductive layer, the first opening, and the second opening;
- forming a third opening in the conductive layer and vertically spaced from the first gate dielectric structure, wherein forming the third opening comprises performing an etching process on the conductive layer to remove a portion of the conductive layer overlying the first gate dielectric structure, and wherein the etching process is performed with the patterned masking layer in place over the upper surface of the conductive layer;
- forming a dishing prevention layer over the conductive layer and in the third opening;
- and
- performing a chemical-mechanical polishing (CMP) process on the dishing prevention layer and the conductive layer, thereby forming a first gate electrode structure overlying the first gate dielectric structure, a second gate electrode structure overlying the second gate dielectric structure, and a dishing prevention structure embedded in the first gate electrode structure.
6 more elements
Dependencies are inferred from the claim text.