Latch circuit and memory device including the same
AssigneeSK hynix Inc.
InventorWoo Hyun PAIK
Life of this patent
Estimating the term…
Abstract
A memory device includes a latch circuit suitable for storing an input address as a first latch address in response to a first latch signal, and storing an address, selected between the input address and the first latch address, as a second latch address in response to a second latch signal, a test determining circuit suitable for determining whether a memory cell fail occurs, based on test data, and generating a detection signal corresponding to the determination result, in response to a test mode signal, and a control signal generation circuit suitable for comparing the input address to the first and second latch addresses in response to the detection signal, and selectively enabling the first and second latch signals according to the comparison result.
Claims21
A memory device comprising:
- a latch circuit suitable for storing an input address as a first latch address in response to a first latch signal, and storing an address, selected between the input address and the first latch address, as a second latch address in response to a second latch signal;
- a test determining circuit suitable for determining whether a memory cell fail occurs, based on test data, and generating a detection signal corresponding to the determination result, in response to a test mode signal;
- and
- a control signal generation circuit suitable for comparing the input address to the first and second latch addresses in response to the detection signal, and selectively enabling the first and second latch signals according to the comparison result.
A memory device comprising:
- a refresh control circuit suitable for generating an input signal and an output signal according to a target refresh operation;
- a test determining circuit suitable for determining whether a memory cell fail occurs, based on test data, and generating a detection signal based on the determination, in response to a test mode signal;
- and
- a control signal generation circuit suitable for, while transmitting the input signal and the output signal as a first latch signal and a second latch signal, respectively, comparing an input address to a first latch address and a second latch address when the detection signal is enabled, and selectively enabling the first and second latch signals according to the comparison result.
A memory device comprising:
- a memory cell array including a plurality of memory cells;
- a test determining circuit suitable for determining whether a fail of one or more memory cells among the plurality of memory cells occurs and generating a detection signal corresponding to the determination result, in response to enabling of a test mode signal;
- a refresh control circuit suitable for generating input and output signals associated with a target refresh operation;
- a control signal generation circuit suitable for receiving an input address and the input and output signals,
- in response to disabling of the test mode signal, generating the input and output signals as first and second latch signals, respectively, and
- in response to enabling of the test mode signal, comparing the input address with first and second latch addresses in response to the detection signal, and selectively enabling one of the first and second latch signals according to the comparison result;
- and
- a latch circuit suitable for receiving the input signal, storing the input address as the first latch address in response to the first latch signal, and storing an address, selected from the input address and the first latch address, as the second latch address in response to the second latch signal.
Dependencies are inferred from the claim text.