Apparatuses, systems, and methods for probabilistic data structures for error tracking
AssigneeMicron Technology, Inc.
InventorSujeet Ayyapureddi
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Abstract
Apparatuses, systems, and methods for probabilistic data structures for error tracking. A memory device may include an error code correction (ECC) circuit which determines if data read from a memory array includes an error. If it does, the row address associated with the read data is provided to an error tracking circuit. The error tracking circuit may use probabilistic data structures, such as multiple count values, each indexed by different hash values of the row address. The count values may be used to determine if a given row address is repeatedly associated with errors. The memory may store these identified problem addresses in a data storage structure for example for diagnostic and/or repair purposes.
Claims20
An apparatus comprising:
- a first hash circuit configured to provide a first count value based on an n-bit hash of a received row address;
- a second hash circuit configured to provide a second count value based on an m-bit hash of the received row address, wherein n and m are different numbers;
- a problem address storage structure configured to store the received row address as a stored problem address if the first count value, the second count value, or combinations thereof exceed a threshold.
An apparatus comprising:
- a memory array comprising a plurality of word lines;
- an error correction code (ECC) circuit configured to identify a row address based on one or more errors in data read from one of the plurality of word lines associated with the row address;
- a first stack comprising a first plurality of registers, each of the first plurality of registers configured to store a count value associated with a first number of the plurality of word lines, wherein the first stack is configured to provide a first count value associated with the identified row address;
- a second stack comprising a second plurality of registers, each of the second plurality of registers configured to store a count value associated with a second number of the plurality of word lines, wherein the second number is different than the first number, and wherein the first stack is configured to provide a second count value associated with the identified row address;
- and
- a problem address storage configured to store the identified row address based on the first count value, the second count value, or combinations thereof.
A method comprising:
- hashing a row address into a first hash comprising a first number of bits;
- changing a first count value associated with a value of the first hash;
- hashing the row address into a second hash comprising a second number of bits, different than the first number of bits;
- changing a second count value associated with a value of the second hash;
- storing the row address in a data stack based on the first count value, the second count value, or combinations thereof.
Dependencies are inferred from the claim text.