Semiconductor memory device and operation method thereof
AssigneeSamsung Electronics Co., Ltd.
InventorsJeongho LEE, Kwangjin LEE, Hee Hyun NAM, Jaeho SHIN, Youngkwang YOO
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Abstract
Disclosed is a method of performing, at a controller, an access to a memory device, which includes transmitting, at the controller, a first command signal, a first address signal, and a first swizzling signal to the memory device, selecting first data bits stored in a memory cell array of the memory device based on the first command signal and the first address signal, and sequentially outputting, at the memory device, at least a part of the first data bits to the controller in a burst manner, based on the first swizzling signal.
Claims20
A method of performing, at a controller, an access to a memory device, the method comprising:
- transmitting, at the controller, a first command signal, a first address signal, and a first swizzling signal to the memory device;
- selecting first data bits stored in a memory cell array of the memory device based on the first command signal and the first address signal;
- and
- sequentially outputting, at the memory device, at least a part of the first data bits to the controller in a burst manner, based on the first swizzling signal.
A memory device comprising:
- a memory cell array including a plurality of memory cells;
- and
- a peripheral circuit configured to:
- receive a first command signal, a first address signal, and a first swizzling signal;
- select first data bits stored in the plurality of memory cells based on the first command signal and the first address signal;
- and
- sequentially output at least a part of the first data bits, which corresponds to the first swizzling signal, from among the first data bits in a burst manner.
A memory system comprising:
- a memory including a plurality of memory cell arrays;
- and
- a controller configured to exchange a data signal with the memory and to control an operation of the memory,
- wherein the memory is configured to:
- receive a first command signal, a first address signal, and a first swizzling signal from the controller;
- and
- sequentially write first data bits included in the data signal to memory cells, which are selected based on the first swizzling signal, from among memory cells corresponding to the first address signal in a burst manner.
Dependencies are inferred from the claim text.