Level Dependent Error Correction Code Protection in Multi-Level Non-Volatile Memory
AssigneeWestern Digital Technologies, Inc.
InventorsNian YANG, Sahil SHARMA, Harish SINGIDI
Life of this patent
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Abstract
A method, apparatus, and system for level dependent error correction code protection in multi-level non-volatile memory. A write command to write data to a non-volatile memory array may be received. At least one multi-level page of multi-level storage cells may be determined for the write data. A coding rate for the write data of the at least one multi-level page may be determined based on an attribute of the at least one multi-level page. An ECC codeword may be generated that satisfies the coding rate and includes the write data. The ECC codeword may then be stored on the at least one multi-level page.
Claims20
A method, comprising:
- receiving a write command to write data to a non-volatile memory array;
- determining a multi-level page of multi-level storage cells for write data of the write command;
- determining a coding rate for write data of at least one multi-level page based on an attribute of the at least one multi-level page;
- generating an ECC codeword that satisfies the coding rate and includes the write data;
- and
- storing the ECC codeword on the at least one multi-level page.
An apparatus, comprising:
- an address allocator configured to determine a multi-level page to store a set of data blocks associated with a set of write commands;
- and
- a packetizer configured to:
- combine the set of data blocks into a payload for an ECC codeword;
- change a payload size for the payload in response to a reliability attribute of the determined multi-level page satisfying a threshold;
- and
- signal the changed payload size to an error correction code encoder configured to generate the ECC codeword.
A system, comprising:
- a non-volatile memory array comprising Quad-level Cell (QLC) memory cells;
- and
- a storage controller comprising:
- a flash translation layer configured to:
- convert a logical block address (LBA) of a storage command into a physical block address (PBA) assigned to a multi-level page of QLC memory cells;
- and
- associate write data of a plurality of write commands with the multi-level page, the multi-level page having a type selected from the group consisting of a lower multi-level page, a middle multi-level page, an upper multi-level page, and a top multi-level page;
- an error correction code encoder configured to:
- generate ECC codewords for the write data assigned to the multi-level page;
- adjust an ECC strength for the generated ECC codewords in response to the multi-level page comprising at least one type;
- and
- a read/write circuit configured to store the ECC codewords on the multi-level page in response to write commands.
Dependencies are inferred from the claim text.