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US 2022/0068415 A1Published application
Latch circuits with improved single event upset immunity and related systems, apparatuses, and methods
AssigneeMicron Technology, Inc.
InventorLiang Liu
Life of this patent
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Abstract
Latch circuits with improved single event upset immunity and related systems, apparatuses, and methods are disclosed. An apparatus includes a dual interlock storage cell (DICE) latch circuit including a first input node corresponding to a first path and a second input node corresponding to a second path. The first input node is electrically isolated from the second input node.
Claims20
An apparatus, comprising:
- a dual interlocked storage cell (DICE) latch circuit including a first input node corresponding to a first path and a second input node corresponding to a second path;
- a first driver circuit electrically connected to the first input node, the first driver circuit configured to receive an input signal and drive a first input signal to the first input node responsive to the input signal;
- and
- a second driver circuit electrically connected to the second input node, the second driver circuit configured to receive the input signal and drive a second input signal to the second input node responsive to the input signal.
1 more element
A method of operating a dual interlocked storage cell (DICE) latch circuit, the method comprising:
- asserting control signals of the DICE latch circuit to operate the DICE latch circuit in a read state;
- applying an input signal to inputs of a first driver circuit and a second driver circuit;
- providing a first input signal to a first input node of the DICE latch circuit responsive to the input signal;
- providing a second input signal to a second input node of the DICE latch circuit responsive to the input signal, the first input node electrically isolated from the second input node;
- and
- latching the first input signal and the second input signal to a first output node and a second output node, respectively, of the DICE latch circuit.
3 more elements
A computing system, comprising:
- one or more processors;
- and
- one or more memory devices electrically connected to the one or more processors, the one or more memory devices including:
- a dual interlocked storage cell (DICE) latch circuit including:
- a first input node;
- and
- a second input node, the second input node electrically isolated from the first input node.
4 more elements
Dependencies are inferred from the claim text.