Memory system

A memory system comprising:

• a semiconductor memory device;
• and
• a memory controller configured to control a read operation in the semiconductor memory device,
• wherein the semiconductor memory device includes:
• first and second memory cells stacked above a substrate;
• a first word line coupled to the first and second memory cells;
• a first bit line coupled to the first memory cell;
• and
• a second bit line coupled to the second memory cell, and
• in the read operation of the first and second memory cells corresponding to a first state, a first sense timing at which data is read from the first memory cell via the first bit line differs from a second sense timing at which data is read from the second memory cell via the second bit line.

A memory system comprising:

• a semiconductor memory device;
• and
• a memory controller configured to control a read operation in the semiconductor memory device,
• wherein the semiconductor memory device includes:
• first and second memory cells stacked above a substrate;
• a first word line coupled to the first and second memory cells;
• a first bit line coupled to the first memory cell;
• and
• a second bit line coupled to the second memory cell, and
• in the read operation of the first and second memory cells corresponding to a first state, a first voltage is applied to the first bit line, and a second voltage differing from the first voltage is applied to the second bit line.

A memory system comprising:

• a semiconductor memory device;
• and
• a memory controller configured to control a read operation in the semiconductor memory device,
• wherein the semiconductor memory device includes:
• first and second memory cells stacked above a substrate;
• a first word line coupled to the first and second memory cells;
• a first bit line coupled to the first memory cell;
• a second bit line coupled to the second memory cell;
• a first source line coupled to the first memory cell;
• and
• a second source line coupled to the second memory cell, and
• in the read operation of the first and second memory cells corresponding to a first state, a first voltage is applied to the first source line, and a second voltage differing from the first voltage is applied to the second source line.