Memory device and operating method thereof
AssigneeSK hynix Inc.
InventorsJae Hyeon SHIN, Tae Ho KIM, In Gon YANG, Sungmook LIM
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AssigneeSK hynix Inc.
InventorsJae Hyeon SHIN, Tae Ho KIM, In Gon YANG, Sungmook LIM
Estimating the term…
A memory device capable of reducing a peak current includes a plurality of memory cell strings each including a plurality of memory cells connected between a common source line and a bit line, a source select line connected between the common source line and the plurality of memory cells, and a drain select line connected between the bit line and the plurality of memory cells. A method for operating the memory device includes: precharging channel regions of a plurality of memory cell strings through a common source line; and setting a bit line voltage applied to the bit line, after starting precharging the channel regions of the plurality of memory cell strings, while the channel regions of the plurality of memory cell strings are being precharged.
A method for operating a memory device including a plurality of memory cell strings each including a plurality of memory cells connected between a common source line and a bit line, a source select line connected between the common source line and the plurality of memory cells, and a drain select line connected between the bit line and the plurality of memory cells, the method comprising:
A memory device comprising:
A method for operating a memory device including a plurality of memory cell strings each including a plurality of memory cells connected between a common source line and a bit line, a source select line connected between the common source line and the plurality of memory cells, and a drain select line connected between the bit line and the plurality of memory cells, the method comprising:
Dependencies are inferred from the claim text.