Memory cell and operating method of memory cell
AssigneeSK hynix Inc.
InventorJae Hyun HAN
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Abstract
A memory cell includes a first electrode, a second electrode, a variable resistance layer located between the first electrode and the second electrode, and a ferroelectric layer located between the variable resistance layer and the second electrode, wherein the variable resistance layer is maintained in an amorphous state during a program operation.
Claims16
A memory cell, comprising:
- a first electrode;
- a second electrode;
- a variable resistance layer located between the first electrode and the second electrode;
- and
- a ferroelectric layer located between the variable resistance layer and the second electrode,
- wherein the variable resistance layer is maintained in an amorphous state during a program operation.
A method of operating a memory cell including a first electrode, a second electrode, a variable resistance layer located between the first electrode and the second electrode, and a ferroelectric layer located between the variable resistance layer and the second electrode, the method comprising:
- applying a positive program voltage to the first electrode, wherein the positive program voltage causes polarization of the ferroelectric layer;
- and
- applying a read voltage that does not polarize the ferroelectric layer to the memory cell.
A method of operating a memory cell including a first electrode, a second electrode, a switching layer located between the first electrode and the second electrode, and a ferroelectric layer located between the switching layer and the second electrode, the method comprising:
- applying a positive program voltage to the first electrode, wherein the positive program voltage causes polarization of the ferroelectric layer;
- and
- applying a read voltage that does not polarize the ferroelectric layer to the memory cell.
Dependencies are inferred from the claim text.